Generally, semiconductor devices are classified as horizontal devices having electrodes formed on one side of the semiconductor substrate, or as vertical devices having electrodes on both sides of the semiconductor substrate. In a vertical semiconductor device, the direction of flow of a drift current when the device is turned on and the expansion direction of a depletion layer caused by a reverse bias voltage when the device is turned off are same.
A semiconductor indicated herein with “n” or “p” at the head means that electrons or holes are the majority carriers of the semiconductor. “+” or “−” that is appended to “n” or “p” like “n+” and “n−” represents a relatively higher concentration or a relatively lower concentration with respect to an impurity concentration of a semiconductor that is not attached thereto.
FIG. 92 is a cross-sectional diagram of an active portion of a conventional planar n-channel MOSFET. As depicted in FIG. 92, the conventional planar n-channel vertical MOSFET 110 has an n− drift layer 2 that is disposed on an anterior side of an n-type low-resistance layer 1. In a surface layer of the n− drift layer 2, a p− well region 10 is provided. In a surface layer of the p− well region 10, n source regions 11 are selectively provided. Between the n source regions 11 in the surface layer of the p− well region 10, p-type high-concentration regions 13 are disposed on a region sandwiched by the n source regions 11 and the n− drift layer 2 in the p− well region 10, a gate electrode 9 is provided through a gate insulating film 3a. An inter-layer insulating film 12 is disposed to cover the gate electrode 9. A source electrode 14 is disposed to contact the n source region 11 and the p-type high-concentration region 13. The source electrode 14 is insulated by the inter-layer insulating film 12 from the gate electrode 9. A protective film 15 is disposed on the source electrode 14. A drain electrode 16 is disposed on a posterior side of the n-type low-resistance layer 1. In the conventional planar n-channel MOSFET, an n counter layer may be provided in the surface layer of the n− drift layer 2.
A manufacturing process of the conventional planar n-channel MOSFET will be described. FIGS. 93 to 99 are diagrams for sequentially explaining the manufacturing processes of the conventional planar n-channel MOSFET. As depicted in FIG. 93, for the conventional planar n-channel MOSFET, the n− drift layer 2 is first formed by, for example, epitaxial growth on the anterior side of the n-type low-resistance layer 1. The semiconductor substrate having the n− drift layer 2 formed on the anterior side of the n-type low-resistance layer 1 is referred to as “semiconductor substrate”. The gate insulating film 3a is formed on the n− drift layer 2. Conductive poly-silicon 8 is deposited on the gate insulating film 3a. The n counter layer may be formed by implanting boron ions into the surface of the n− drift layer 2.
As depicted in FIG. 94, the gate insulating film 3a and the poly-silicon 8 are etched using a first mask not depicted and formed by pattern-forming with a resist film and thereby, the gate electrode 9 is formed. After removing the first mask, using the gate electrode 9 as a mask, impurity ions are implanted into the regions having the n− drift layer 2 exposed therein and thereby, the p− well region 10 is formed.
As depicted in FIG. 95, impurity ions are implanted into an opening 82 of a second mask 81 formed by pattern-forming with a resist film and thereby, a p-type high-concentration region 13 is formed in the surface layer of the p− well region 10. The second mask 81 is formed such that the edge of the opening 82 is about 0.5 to 2.0 micrometers away from the gate electrode 9. As depicted in FIG. 96, the second mask 81 is removed.
As depicted in FIG. 97, a third mask 83 is formed by pattern-forming with a resist film and ion implantation is executed using the gate electrode 9 and the third mask 83 as a mask and thereby, the n source layers 11 are selectively formed in the surface layer of the p-type high-concentration region 13. As depicted in FIG. 98, the third mask 83 is removed.
At this time, a surface along a long side of a region sandwiched by the n source regions 11 and the n− drift layer 2 of the p− well region 10 is a channel region. The channel region is a region of an inversion layer that is formed in the surface layer of the p− well region 10 when a gate voltage equal to or higher than a threshold voltage is applied to the gate electrode 9.
The insulating layer 12 is deposited from the anterior side of the semiconductor substrate. Using a fourth mask not depicted formed by pattern-forming with a resist film, the insulating film 12 is selectively removed not to expose the gate electrode 9 and thereby, openings 85 are formed. Therefore, in the openings 85, the p-type high-concentration region 13 and the n source regions 11 are exposed.
As depicted in FIG. 99, the source electrode (Al—Si) 14 is formed to commonly contact the p-type high-concentration region 13 and the n source regions 11 in the openings 85. The protective film 15 is formed on the source electrode 14 and the drain electrode 16 is formed on the posterior side of the semiconductor substrate. Thereby, the planar n-channel MOSFET is completed.
However, according to the manufacturing method of the conventional planar n-channel MOSFET, one mask is used in each one ion implanting session. Therefore, to manufacture the planar n-channel MOSFET, four masks in total, the first to the fourth masks, are necessary. As described, when many pattern-forming sessions for masks are executed, the number of processes becomes large and therefore, the cost for the manufacture becomes high. When the number of sessions that use masks is large, the alignment precision is degraded and therefore, the tolerance to variation among devices must be increased. Therefore, finer processing becomes difficult. Heat treatment is applied twice between the formation of the gate electrode using the first mask and the formation of the inter-layer insulating film and therefore, loads are applied to the gate film.
To solve these problems, a method has been proposed of forming the source region and the drain region using the same mask when a horizontal semiconductor device is formed (see, e.g., Patent Document 1). The source region and the drain region of the horizontal semiconductor device: are both formed on the anterior side of a semiconductor substrate; are of the same conductivity; have the same impurity concentration; and therefore, may simultaneously be formed. However, in a vertical semiconductor device, the source region and the drain region are formed separately from each other on respective sides of a semiconductor substrate. Therefore, this method can not be applied to the vertical semiconductor device.
Thus, for the vertical semiconductor device, a method has been proposed of forming the p− well region 10 and the n source region 11 using the same nitride film (Si3N4) mask after forming the gate electrode 9 (see, e.g., Patent Document 2). According to this method, to form a LOCOS (Local Oxidation of Silicon) oxide film to be used as a mask when the p-type high-concentration region 13 is formed after the n source region 11 is formed, selective oxidation is executed using a nitride film mask and thereby, an oxide film is thickly formed in a region having no nitride film mask formed therein on the anterior side of the semiconductor substrate. Patterning is executed for this oxide film and thereby, the LOCOS oxide film to be used as the mask is formed.
A voltage-resistant structure portion of the conventional planar n-channel MOSFET will be described. A guard ring technique will be described that is one of voltage-resistant structure techniques for a semiconductor apparatus. FIG. 100 is a diagram for explaining the cross-sectional structure of the voltage-resistant structure portion of the conventional planar n-channel MOSFET. FIG. 101 is a diagram for explaining in detail the cross-sectional structure of active portion vicinity 211 of a voltage-resistant structure portion 210 of the conventional planar n-channel MOSFET. As depicted in FIG. 100, the voltage-resistant structure portion 210 of the conventional planar n-channel MOSFET is disposed on the outer edge of the active portion 110. The voltage-resistant structure portion 210 is provided with a loop-shaped p− region 10b in the surface layer of the n− drift layer 2 such that the p− region 10b surrounds the p− well region 10. The p− region 10b is connected to the p− well region 10. The impurity concentration of the p− region 10b is lower than the impurity concentration of the p− well region 10. The diffusion depth of the p− region 10b is deeper than the diffusion depth of the p− well region 10. A p guard ring 10c is provided in a loop shape to surround the p− region 10b. An end of the p guard ring 10c is connected to an edge of the p− region 10b. The impurity concentration of the p guard ring 10c is equal to the impurity concentration of the p− region 10b. The diffusion depth of the p guard ring 10c is equal to the diffusion depth of the p− region 10b (see, e.g., Patent Document 3). The voltage-resistant structure is configured by employing a semiconductor apparatus configuration formed by combining a RESURF (REduced SURface Field) structure and a guard ring (field-limiting ring) structure, without using any field plate that reduces the conductivity at a low temperature, as the technique described in Patent Document 3.
As depicted in FIG. 101, an outer edge of the active portion 110 is selectively provided with p-type high-concentration regions 13 in the surface layer of the p− well region 10. The gate electrode 9 is provided through the gate insulating film 3a on a region sandwiched by the p-type high-concentration regions 13 and the n− drift layer 2 of the p− well region 10. Other configurations on the outer edge of the active portion 110 are same as those of the active portion 110 of the semiconductor apparatus depicted in FIG. 92.
A surface layer of the p guard ring 10c is selectively provided with the p− well regions 10. Field plate electrodes 9a are selectively provided through an insulating film 25 on the p− region 10b and the p guard ring 10c. An opening is provided for the insulating film 25. The opening has exposed therein the p− well regions 10 that are provided for the surface layer of the p guard ring 10c. Inter-layer insulating films 19 are selectively disposed on the surface of the field plate electrodes 9a such that a portion of each of the field plate electrodes 9a is exposed. A metal film 14a is disposed to contact the field plate electrodes 9a and the p− well region 10 that is exposed in the opening of the insulating film 25. The protective film 15 is disposed on the source electrode 14 and the metal film 14a. The drain electrode 16 is disposed on the posterior side of the n-type low-resistance layer 1.
In the planar structure not depicted of the chip having the active portion and the voltage-resistant structure portion of the conventional planar n-channel MOSFET, the active portion 110 is provided in the central portion of the chip and the voltage-resistant structure portion 210 is disposed on the outer circumference of the active portion 110. A p stopper region 77, a p contact region 73, and a contact opening 76 of the voltage-resistant structure portion 210 (see FIG. 100) are disposed on the entire circumference of the voltage-resistant structure portion to surround the p guard ring 10c on the outer circumference of the chip.
Manufacturing processes of the guard ring of the conventional planar n-channel MOSFET will be described. FIGS. 102 to 110 are diagrams for sequentially explaining the manufacturing processes of the guard ring of the conventional planar n-channel MOSFET. As depicted in FIG. 102, for the voltage-resistant structure portion of the conventional planar n-channel MOSFET, an insulating film 24 is formed on the semiconductor substrate on which the n− drift layer 2 is formed by, for example, epitaxial growth on the anterior side of the n-type low-resistance layer 1. As depicted in FIG. 103, the insulating film 24 is etched using a sixth mask not depicted and formed by pattern-forming with a resist film using a photo-mask and thereby, the surface of the n− drift layer 2 is selectively exposed.
Using the insulating film 24 as a mask, impurity ions are implanted into the regions having the n− drift layer 2 exposed therein and thereby, the p− region 10b and the p guard ring 10c are formed. As depicted in FIG. 104, leaving the insulating film 24 as it is, the entire anterior face of the semiconductor substrate is oxidized and thereby, an insulating film 25 is formed. As depicted in FIG. 105, the insulating film 25 is etched using a seventh mask not depicted and formed by pattern-forming with a resist film using a photo-mask and thereby, the surface of the n− drift layer 2 and a portion of the surface of the p guard ring 10c are selectively exposed.
As depicted in FIG. 106, the gate insulating film 3a is formed on the anterior side of the semiconductor substrate and the conductive poly-silicon 8 is deposited on the gate insulating film 3a. As depicted in FIG. 107, the gate insulating film 3a and the poly-silicon 8 are etched using an eighth mask not depicted and formed by pattern-forming with a resist film using a photo-mask and thereby, the gate electrode 9 and the field plate electrode 9a are formed. After removing the eighth mask, impurity ions are implanted into the regions having the n− drift layer 2 exposed therein using the gate electrode 9 and the insulting film 25 as a mask and thereby, the p− well region 10 is formed. Simultaneously, impurity ions are implanted into the region having the p guard ring 10c exposed therein using the gate electrode 9 and the field plate electrode 9a as a mask and thereby, the p− well region 10 is formed.
As depicted in FIG. 108, impurity ions are implanted into an opening 86 of a ninth mask 301 formed by pattern-forming with a resist film using a photo-mask and thereby, the p-type high-concentration region 13 is formed in the surface layer of the p− well region 10. At this time, the ninth mask 301 is formed such that the edge of the opening 86 is about 0.5 to 2.0 micrometers away from the gate electrode 9.
As depicted in FIG. 109, the ninth mask 301 is removed and an insulating film is deposited from the anterior side of the semiconductor substrate. Using a tenth mask not depicted and formed by pattern-forming with a resist film using a photo-mask, the insulating film is selectively removed such that the gate electrode 9 is not exposed and the field plate electrode 9a is partially exposed and thereby, openings 87 and 88 are formed. Thereby, the insulting film 12 is formed to cover the gate electrode 9 and the insulating film 19 is formed such that the field plate electrode 9a is partially exposed. The p-type high-concentration region 13 is exposed in the opening 87, and the p− well region 10 is exposed in the opening 88.
As depicted in FIG. 110, the source electrode (Al—Si) 14 is formed to be electrically connected in the opening 87 to the p− well region 10 through the p-type high-concentration region 13. The metal film (Al—Si) 14a is formed to contact the p− well region 10 in the opening 88. The protective film 15 is formed on the source electrode 14 and the metal film 14a and the drain electrode 16 is formed on the posterior side of the semiconductor substrate and thereby, the guard ring of the planar n-channel MOSFET as depicted in FIG. 101 is completed.